Interfacing circuits that receive signals at TTL input levels, evaluate the signal levels, and produce corresponding output signals at CMOS levels are necessary for use where TTL to CMOS buffering is required. Existing circuits of this type are typically used as input buffers to CMOS microprocessors requiring TTL compatibility but suffer the disadvantage of drawing a considerable amount of current from the associated microprocessor power source. Another problem encountered with prior art buffers of this type is that of device threshold sensitivity, or the ability of the buffer circuitry to evaluate with accuracy the state of a signal near the threshold voltage level of the TTL devices. The present buffer circuit consumes substantially no D.C. power and device threshold sensitivity is virtually eliminated.